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ltc2872 1 2872f typical a pplica t ions descrip t ion rs232/rs485 dual multiprotocol transceiver with integrated termination the ltc ? 2872 is a robust pin-configurable transceiver that supports rs232, rs485, and rs422 standards while operating on a single 3v to 5.5v supply. the ltc2872 can be configured as four rs232 single-ended transceivers or two rs485 differential transceivers, or combinations of both, on shared i/o lines. pin-controlled integrated termination resistors allow for easy interface reconfiguration, eliminating external resistors and control relays. half-duplex switches allow four-wire and two-wire rs485 configurations. loopback mode steers the driver inputs to the receiver outputs for diagnostic self-test. the rs485 receivers support up to 256 nodes per bus, and feature full failsafe operation for floating, shorted or terminated inputs. an integrated dc/dc boost converter uses a small induc - tor and one capacitor, eliminating the need for multiple supplies for driving rs232 levels. l , lt, ltc, ltm, linear technology, the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. rs485 mode with duplex control fea t ures a pplica t ions n four rs232 and two rs485 t ransceivers n 3v to 5.5v supply voltage n 20mbps rs485 and 500kbps rs232 n automatic selection of integrated rs485 (120) and rs232 (5k) termination resistors n half-/full-duplex rs485 switching n logic loopback mode n high esd: 16kv on line i/o n 1.7v to 5.5v logic interface n supports up to 256 rs485 nodes n rs485 receiver full failsafe eliminates uart lockup n available in 38-pin 5mm 7mm qfn package n flexible rs232/rs485/rs422 interface n software selectable multiprotocol interface ports n point-of-sale terminals n cable repeaters n protocol translators n profibus-dp networks rs232 mode mixed mode with rs485 termination 2872 ta01 ltc2872 3v to 5.5v 1.7v to v cc rs485 termination h/f dy1 2.2f y1 z1 a2 b2 a1 b1 ra1 dy2 ra2 v dd v ee dy1 dy2 rb2 ra2 dz2 rb1 ra1 dz1 y1 b2 a2 z1 y2 z2 a1 b1 ltc2872 dy2 rb2 ra2 dz2 b2 a2 y2 z2 y1 z1 dy1 te485-1 ltc2872 120 onoff rs485 duplex halffull y2 z2 a1 b1 ra1 120 v l v cc cap 470nf 22h 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f sw 3v to 5.5v 1.7v to v cc 2.2f v dd v ee v l v cc cap 470nf 22h sw 3v to 5.5v 1.7v to v cc 2.2f v dd v ee v l v cc cap 470nf 22h sw
ltc2872 2 2872f p in c on f igura t ion a bsolu t e maxi m u m r a t ings input supplies v cc , v l ..................................................... C0 .3v to 7v generated supplies v dd ................................................ v cc C 0.3v to 7.5v v ee ......................................................... 0. 3v to C7.5v v dd C v ee .............................................................. 15v s w ........................................... C 0.3v to (v dd + 0.3v) cap ............................................. 0 .3v to (v ee C 0.3v) a1, a2, b1, b2, y1, y2, z1, z2 ...................... C 15v to 15v dy1, dy2, dz1, dz2, rxen1 , rxen2 , dxen1, dxen2, lb, h/ f , te485_1, te485_2, 485/ 232 _1, 485/ 232 _2 ................................ C 0.3v to 7v fen, ra1, ra2, rb1, rb2 ............... C 0.3v to (v l + 0.3v) differential enabled terminator voltage (a1-b1 or a2-b2 or y1-z1 or y2-z2) ..................... 6v operating temperature ltc2872c ................................................ 0 c to 70c ltc2872i ............................................. C 40c to 85c storage temperature range .................. C 65c to 125c (note 1) 13 14 15 16 top view 39 v ee uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1v cc a1 b1 y1 gnd z1 dy1 dz1 rxen1 dxen1 te485_1 te485_2 v cc a2 b2 y2 gnd z2 dy2 dz2 rxen2 dxen2 v cc v dd rb1 ra1 lb v l gnd ra2 rb2 485/232_1 485/232_2 h/f fen cap gnd sw 23 22 21 20 9 10 11 12 t jmax = 125c, v ja = 34.7c/w exposed pad (pin #39) is v ee , must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2872cuhf#pbf ltc2872cuhf#trpbf 2872 38-lead (5mm w 7mm) plastic qfn 0c to 70c ltc2872iuhf#pbf ltc2872iuhf#trpbf 2872 38-lead (5mm w 7mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc2872 3 2872f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = v l = 3.3v, te485_1 = te485_2 = 0v, lb = 0v unless otherwise noted. symbol parameter conditions min typ max units power supply v cc supply voltage operating range l 3 5.5 v v l logic supply voltage operating range v l v cc l 1.7 v cc v v cc supply current in shutdown mode rxen1 = rxen2 = v l , dxen1 = dxen2 = fen = h/f = 0v l 8 60 a v cc supply current in rs485 transceiver mode (outputs unloaded) (note 3) 485/232_1 = 485/232_2 = dxen1 = dxen2 = v l , rxen1 = rxen2 = 0v l 4.5 7 ma v cc supply current in rs232 transceiver mode (outputs unloaded) (note 3) dxen1 = dxen2 = v l ; 485/232_1 = 485/232_2 = rxen1 = rxen2 = 0v l 5.5 8 ma v l supply current in rs485 or rs232 transceive mode (outputs unloaded) dxen1 = dxen2 = v l , rxen1 = rxen2 = 0v l 0 5 a rs485 drivers |v od | differential output voltage r l = , v cc = 3v (figure 1) r l = 27?, v cc = 4.5v (figure 1) r l = 27?, v cc = 3v (figure 1) r l = 50?, v cc = 3.13v (figure 1) l l l l 2.1 1.5 2 6 v cc v cc v cc v v v v ?|v od | difference in magnitude of differential output voltage for complementary output states r l = 27?, v cc = 3v (figure 1) r l = 50?, v cc = 3.13v (figure 1) l l 0.2 0.2 v v v oc common mode output voltage r l = 27? or 50? (figure 1) l 3 v ?|v oc | difference in magnitude of common mode output voltage for complementary output states r l = 27? or 50? (figure 1) l 0.2 v i ozd485 three-state (high impedance) output current v out = 12v or C7v, v cc = 0v or 3.3v (figure 2) l C100 125 a i osd485 maximum short-circuit current C7v v out 12v (figure 2) l C250 250 ma rs485 receiver i in485 input current v in = 12v or C7v, v cc = 0v or 3.3v (figure 3) (note 5) l C100 125 a r in485 input resistance v in = 12v or C7v, v cc = 0v or 3.3v (figure 3) (note 5) 125 k differential input signal threshold voltage (aCb) C7v (a or b) 12 (note 5) l 200 mv differential input signal hysteresis b = 0v (notes 3, 5) 190 mv differential input dc failsafe threshold voltage (aCb) C7v (a or b) 12 (note 5) l C200 C65 0 mv differential input dc failsafe hysteresis b = 0v (note 5) 30 mv v ol output low voltage output low, i(ra) = 3ma (sinking), 3v v l 5.5v l 0.4 v output low, i(ra) = 1ma (sinking), 1.7v v l < 3v l 0.4 v v oh output high voltage output high, i(ra) = C3ma (sourcing), 3v v l 5.5v l v l C 0.4 v output high, i(ra) = C1ma (sourcing), 1.7v v l < 3v l v l C 0.4 v three-state (high impedance) output current 0v ra v l , v l = 5.5v l 0 5 a short-circuit output current 0v ra v l , v l = 5.5v l 135 ma r term terminating resistor te485 = v l , aCb = 2v, b = C7v, 0v, 10v (figure 8) (note 5) l 108 120 156
ltc2872 4 2872f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = v l = 3.3v, te485_1 = te485_2 = 0v, lb = 0v unless otherwise noted. symbol parameter conditions min typ max units rs232 driver v old output low voltage r l = 3k, v ee C6v l C5 C5.7 v ee v v ohd output high voltage r l = 3k, v dd 6.5v l 5 6.2 v dd v three-state (high impedance) output current y or z = 15v l 156 a output short-circuit current y or z = 0v l 35 90 ma rs232 receiver input threshold voltage l 0.6 1.5 2.5 v input hysteresis l 0.1 0.4 1.0 v output low voltage i(ra, rb) = 1ma (sinking), 1.7v v l 5.5v l 0.4 v output high voltage i(ra, rb) = C1ma (sourcing), 1.7v v l 5.5v l v l C 0.4 v input resistance C15v (a, b) 15v, receiver enabled l 3 5 7 k three-state (high impedance) output current 0v (ra, rb) v l l 0 5 a output short-circuit current v l = 5.5v, 0v (ra, rb) v l l 25 50 ma logic inputs threshold voltage l 0.4 0.75? v l v input current l 0 5 a power supply generator v dd regulated v dd output voltage rs232 drivers enabled, outputs loaded with r l = 3k to gnd, dy1 = dy2 = v l , dz1 = dz2 = 0v (note 3) 7 v v ee regulated v ee output voltage C6.3 v esd interface pins (a, b, y, z) human body model to gnd or v cc , powered or unpowered (note 7) 16 kv all other pins human body model (note 7) 4 kv
ltc2872 5 2872f s wi t ching c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = v l = 3.3v, te485_1 = te485_2 = 0v, lb = 0v unless otherwise noted. v l v cc . symbol parameter conditions min typ max units rs485 ac characteristics maximum data rate (note 3) l 20 mbps t plhd485 t phld485 driver propagation delay r diff = 54, c l = 100pf (figure 4) l 20 70 ns driver propagation delay difference |t plhd485 C t phld485 | r diff = 54, c l = 100pf (figure 4) l 1 6 ns t skewd485 driver skew (y to z) r diff = 54, c l = 100pf (figure 4) l 1.5 8 ns t rd485 , t fd485 driver rise or fall time r diff = 54, c l = 100pf (figure 4) l 7.6 15 ns t zld485 , t zhd485 , t lzd485 , t hzd485 driver output enable or disable time fen = v l , r l = 500?, c l = 50pf (figure 5) l 120 ns t zhsd485 , t zlsd485 driver enable from shutdown fen = 0v, r l = 500?, c l = 50pf (figure 5) l 0.2 2 ms t plhr485 , t phlr485 receiver input to output c l = 15pf, v cm = 1.5v, |aCb| = 1.5v, (figure 6) (note 5) l 55 85 ns t skewr485 differential receiver skew |t plhr485 C t phlr485 | c l = 15pf (figure 6) l 1 9 ns t rr485 , t fr485 receiver output rise or fall time c l = 15pf (figure 6) l 3 15 ns t zlr485 , t zhr485 t lzr485 , t hzr485 receiver output enable or disable time fen = v l , r l = 1k, c l = 15pf (figure 7) l 30 85 ns t rten485 , t rtz485 termination enable or disable time fen = v l , v b = 0v, v ab = 2v (figure 8) (note 5) l 100 s rs232 ac characteristics maximum data rate r l = 3k, c l = 2500pf, r l = 3k, c l = 500pf (note 3) l l 100 500 kbps kbps driver slew rate (figure 9) r l = 3k, c l = 2500pf r l = 3k, c l = 50pf l l 4 30 v/s v/s t phld232 , t plhd232 driver propagation delay r l = 3k, c l = 50pf (figure 9) l 1 2 s t skewd232 driver skew r l = 3k, c l = 50pf (figure 9) 50 ns t zld232 , t zhd232 t lzd232 , t hzd232 driver output enable or disable time fen = v l , r l = 3k, c l = 50pf (figure 10) l 0.4 2 s t phlr232 , t plhr232 receiver propagation delay c l = 150pf (figure 11) l 60 200 ns t skewr232 receiver skew c l = 150pf (figure 11) 25 ns t rr232 , t fr232 receiver rise or fall time c l = 150pf (figure 11) l 60 200 ns t zlr232 , t zhr232 , t lzr232 , t hzr232 receiver output enable or disable time fen = v l , r l = 1k, c l = 150pf (figure 12) l 0.7 2 s power supply generator v dd /v ee supply rise time fen = , (notes 3 and 4) l 0.2 2 ms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to device ground unless otherwise specified. note 3. guaranteed by other measured parameters and not tested directly. note 4. time from fen until v dd 5v and v ee C5v. external components as shown in typical application. note 5. condition applies to a, b for h/f = 0v, and y, z for h/f = v l . note 6. this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. overtemperature protection activates at a junction temperature exceeding 150c. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. note 7. guaranteed by design and not subject to production test.
ltc2872 6 2872f typical p er f or m ance c harac t eris t ics v cc supply current vs rs232 data rate v cc supply current vs supply voltage for rs485 at maximum data rate rs485 driver differential output voltage vs temperature rs485 driver propagation delay vs temperature rs485 driver short-circuit current vs short-circuit voltage rs485 driver and receiver skew vs temperature v cc supply current vs supply voltage in shutdown mode v cc supply current vs supply voltage in fast enable mode v cc supply current vs rs485 data rate input voltage (v) 3 input currenet (a) 30 25 20 15 10 5 0 4.5 5 3.5 2872 g01 5.5 4 h/f low h/f high supply voltage (v) 3 supply current (ma) 4.6 4.2 3.8 3.4 4.4 4.0 3.6 3.2 3.0 5 3.5 2872 g02 5.5 4.54 ?40c 25c 85c data rate (mbps) 0.1 supply current (ma) 200 140 100 60 160 180 120 80 40 20 0 1 2872 g03 100 10 driver and receiver termination enabled termination disabled all rs485 drivers and receivers switching. y tied to a; z tied to b, h/f = 0v, c l = 100pf on y and z to gnd v cc = 5v v cc = 3.3v data rate (kbps) 0 input current (ma) 50 45 35 25 40 30 20 15 10 50 2872 g04 500 100 150 200 250 300 350 450400 all rs232 drivers and receivers switching 2.5nf 2.5nf 0.5nf v cc = 5v v cc = 3.3v 0.5nf 0.05nf 0.05nf supply voltage (v) 3 supply current (ma) 240 220 180 140 200 160 120 100 80 3.5 2872 g05 5.5 4 4.5 5 both rs485 drivers and receivers switching. y tied to a, z tied to b h/f = 0v driver and receiver termination enabled 20mbps, c l = 100pf on y and z to gnd 85c 25c ?40c temperature (c) ?50 voltage (v) 4.5 3.5 2.5 1.5 4.0 3.0 2.0 1.0 0.5 0 50 75 ?25 2872 g06 100 250 r l = 100 r l = 54 r l = 100 r l = 54 v cc = 5v v cc = 3.3v temperature (c) ?50 delay (ns) 50 40 30 20 10 0 50 75 ?25 2872 g07 100 250 v cc = 3.3v, v l = 1.7v v cc = 5v, v l = 1.7v v cc = 3.3v, v l = 3.3v v cc = 5v, v l = 5v short-circuit voltage (v) ?10 short-circuit current (ma) 150 100 0 50 ?50 ?100 ?150 10 ?5 2872 g08 15 50 output low output high v cc = 5v v cc = 3.3v temperature (c) ?50 skew (ns) 3.0 2.5 1.5 2.0 1.0 0.5 0 50 75 ?25 2872 g09 100 250 driver receiver
ltc2872 7 2872f typical p er f or m ance c harac t eris t ics rs485 termination resistance vs temperature rs232 operation at 500kbps rs485 operation at 20mbps rs485 receiver output voltage vs load current rs232 receiver input threshold vs temperature rs232 receiver output voltage vs load current rs232 driver outputs enabling and disabling v dd and v ee powering up rs485 receiver propagation delay vs temperature temperature (c) ?50 delay (ns) 80 70 60 50 40 50 75 ?25 2872 g10 100 250 v cc = 3.3v, v l = 1.7v v cc = 5v, v l = 1.7v v cc = 3.3v, v l = 3.3v v cc = 5v, v l = 5v output current (ma) 0 output voltage (v) 6 5 4 2 3 1 0 8 2 2872 g11 10 64 v l = 5v v l = 3.3v v l = 1.7v temperature (c) ?50 threshold voltage (v) 2.0 1.8 1.6 1.4 1.2 1.0 50 75 ?25 2872 g12 100 250 v cc = 5v v cc = 3.3v input high input low output current (ma) 0 output voltage (v) 6 5 4 2 3 1 0 8 2 2872 g13 10 64 v l = 5v v l = 3.3v v l = 1.7v temperature (c) ?50 resistance () 130 118 116 114 112 110 128 126 124 122 120 50 75 ?25 2872 g14 100 250 v cm = ?7v v cm = 2v v cm = 12v 1s/div wrapping data dout loads: 5k + 50pf 5v/div 2872 g15 dy dz ra rb z y 20ns/div h/f high y, z loads: 120 (diff) + 50pf 1v/div 5v/div 5v/div 2872 g16 dy ra z y 40ns/div 5v/div 2872 g17 dxen fen = vl fen = 0v z y z y 100s/div 5v/div 2v/div 2872 g18 fen v dd v ee
ltc2872 8 2872f p in func t ions v cc (pins 1, 21, 31): input supply (3.0v to 5.5v). tie all three pins together and connect 2.2f capacitor between vcc and gnd. v l (pin 35): logic supply (1.7v to 5.5v) for the receiver outputs, driver inputs, and control inputs. this pin should be bypassed to gnd with a 0.1f capacitor if it is not tied to v cc . v l must be less than or equal to v cc for proper operation. v dd (pin 20): generated positive supply voltage for rs232 driver (7v). connect 2.2f capacitor between v dd and gnd. v ee (pin 39): generated negative supply voltage for rs232 driver (C6.3v). tie all pins together and connect 2.2f capacitor between v ee and gnd. gnd (pins 5, 18, 27, 34): ground. tie all four pins together. cap (pin 17): charge pump capacitor for generated nega- tive supply voltage. connect a 470nf capacitor between cap and sw. sw (pin 19): switch pin. connect 22h inductor between sw and v cc . a1 (pin 2): rs485 differential receiver #1 positive input (full-duplex mode) or rs232 receiver #1a input. a2 (pin 30): rs485 differential receiver #2 positive input (full-duplex mode) or rs232 receiver #2a input. b1 (pin 3): rs485 differential receiver #1 negative input (full-duplex mode) or rs232 receiver #1b input. b2 (pin 29): rs485 differential receiver #1 negative input (full-duplex mode) or rs232 receiver #2b input. ra1 (pin 37): rs485 differential receiver #1 output or rs232 receiver #1a output. ra2 (pin 33): rs485 differential receiver #2 output or rs232 receiver #2a output. rb1 (pin 38): rs232 receiver #1b output. rb2 (pin 32): rs232 receiver #2b output. dy1 (pin 7): rs485 differential driver #1 input or rs232 driver #1y input. dy2 (pin 25): rs485 differential driver #2 input or rs232 driver #2y input. dz1 (pin 8): rs232 driver #1z input. dz2 (pin 24): rs232 driver #2z input. y1 (pin 4): rs485 differential driver #1 positive output or rs232 driver #1y output, rs485 differential receiver #1 positive input (half-duplex mode). y2 (pin 28): rs485 differential driver #2 positive output or rs232 driver #2y output, rs485 differential receiver #2 positive input (half-duplex mode). z1 (pin 6): rs485 differential driver #1 negative output or rs232 driver #1z output, rs485 differential receiver #1 negative input (half-duplex mode). z2 (pin 26): rs485 differential driver #2 negative output or rs232 driver #2z output, rs485 differential receiver #2 negative input (half-duplex mode). 485/232_1 (pin 13): interface select #1 input. a logic low enables rs232 mode and a high enables rs485 mode for transceiver #1. the mode determines which transceiver inputs and outputs are accessible at the ltc2872 pins as well as which is controlled by the driver and receiver enable pins. 485/232_2 (pin 14): interface select #2 input. a logic low enables rs232 mode and a high enables rs485 mode for transceiver #2. the mode determines which transceiver inputs and outputs are accessible at the ltc2872 pins as well as which is controlled by the driver and receiver enable pins. rxen1 (pin 9): receivers #1 enable. a logic high disables rs232 and rs485 receivers in transceiver #1, leaving their outputs hi-z. a logic low enables the rs232 or rs485 receivers in transceiver #1, depending on the state of the interface select input 485/ 232_1. rxen2 (pin 23): receivers #2 enable. a logic high disables rs232 and rs485 receivers in transceiver #2, leaving their outputs hi-z. a logic low enables the rs232 or rs485 receivers in transceiver #2, depending on the state of the interface select input 485/ 232_2.
ltc2872 9 2872f p in func t ions dxen1 (pin 10): drivers #1 enable. a logic low disables the rs232 and rs485 drivers in transceiver #1, leaving their outputs in a hi-z state. a logic high enables the rs232 or rs485 drivers in transceiver #1, depending on the state of the interface select input 485/ 232_1. dxen2 (pin 22): drivers #2 enable. a logic low disables the rs232 and rs485 drivers in transceiver #2, leaving their outputs in a hi-z state. a logic high enables the rs232 or rs485 drivers in transceiver #2, depending on the state of the interface select input 485/ 232_2. te485_1 (pin 11): rs485 termination enable for trans - ceiver #1. a logic high enables a 120? resistor between pins a1 and b1. if dz1 is also high, a 120? resistor is enabled between pins y1 and z1. a logic low on te485_1 opens the resistors, leaving a1/b1 and y1/z1 unterminated, independent of dz1. the differential termination resistors are never enabled in rs232 mode. te485_2 (pin 12): rs485 termination enable for trans - ceiver #2. a logic high enables a 120? resistor between pins a2 and b2. if dz2 is also high, a 120? resistor is enabled between pins y2 and z2. a logic low on te485_2 opens the resistors, leaving a2/b2 and y2/z2 unterminated, independent of dz2. the differential termination resistors are never enabled in rs232 mode. h/f (pin 15): rs485 half-duplex select input for trans- ceivers #1 and #2. a logic low is used for full duplex operation where pins a and b are the receiver inputs and pins y and z are the driver outputs. a logic high is used for half duplex operation where pins y and z are both the receiver inputs and driver outputs and pins a and b do not serve as the receiver inputs. the impedance on a and b and state of differential termination between a and b is independent of the state of h/f. the h/f pin has no effect on rs232 operation. fen (pin 16): fast enable. a logic high enables fast enable mode. in fast enable mode the integrated dc/dc converter is active independent of the state of driver, receiver, and termination enable pins allowing faster circuit enable times than are otherwise possible. a logic low disables fast enable mode leaving the state of the dc/dc converter dependent on the state of driver, receiver, and termina - tion enable control inputs. the dc/dc converter powers down only when fen is low and all drivers, receivers, and terminators are disabled (refer to table 1). lb (pin 36): loopback enable for transceivers #1 and #2. a logic high enables logic loopback diagnostic mode, internally routing the driver input logic levels to the receiver output pins within the same transceiver. this applies to both rs232 channels as well as the rs485 driver/receiver. the targeted receiver must be enabled for the loopback signal to be available on its output. a logic low disables loopback mode. in loopback mode, signals are not inverted from driver inputs to receiver outputs.
ltc2872 10 2872f b lock diagra m 2872 bd control logic drivers transceiver #1 receivers loopback path 0.1f dxen rxen1 te485_1 h/f 485/232_1 dxen2 dy2 dz2 ra2 rb2 rxen2 te485_2 485/232_2 fen lb dy1 dz1 ra1 rb1 gnd b1 y2 z2 a2 b2 a1 port 1 port 2 z1 y1 v ee v dd gnd v cc gnd 1.7v to 5.5v ( v cc ) pulse-skipping boost regulator f = 1.2mhz rt232 rt485 2.2f 22h 470nf 3v to 5.5v 2.2f 2.2f cap sw v cc v l 232 485 232 232 485 232 5k rt232 rt485 125k 5k 125k 125k 120 rt485 120 h/f 125k transceiver #2 35 21 19 17 20 39 18 4 1 5 6 2 3 28 v cc gnd 31 27 26 30 29 34 32 33 24 25 14 12 23 22 38 37 8 7 13 11 9 10 15 36 16
ltc2872 11 2872f tes t c ircui t s figure 1. rs485 driver dc characteristics figure 2. rs485 driver output short-circuit current figure 3. rs485 receiver input current and resistance (note 5) figure 4. rs485 driver timing measurement 2872 f01 driver dy gnd or v l y r l r l z v od + ? v oc + ? 2872 f03 receiver a or b b or a v in i in485 r in485 = v in i in485 + ? 2872 f04 driver dy y z r diff c l c l t plhd485 t skewd485 t plhd485 t rd485 t fd485 90% 0v v od ?v od v l 0v dy y, z y - z 10% 90% 0v 10% 2872 f02 driver y or z dy gnd or v l z or y v out i ozd485 , i osd485 + ?
ltc2872 12 2872f t es t circui t s figure 5. rs485 driver enable and disable timing measurements figure 6. rs485 receiver propagation delay measurements (note 5) figure 7. rs485 receiver enable and disable timing measurements (note 5) 2872 f07 t zlr485 t lzr485 t hzr485 t zhr485 ?v l ?v l v l v ol v l v oh 0v 0v 0.5v rxen ra ra receiver ra rxen 0v to 3v 3v to 0v a r l b v l or gnd c l ?v l 0.5v ?v l 2872 f05 t zld485 , t zlsd485 t lzd485 t hzd485 t zhd485 , t zhsd485 ?v cc ?v cc v l v ol v cc v oh 0v 0v 0.5v dxen y or z z or y driver dy dxen v l or gnd y r l z gnd or v cc v cc or gnd r l c l c l ?v l 0.5v ?v l 2872 f06 receiver v cm v ab /2 a b ra v ab /2 c l t plhr485 t skewr485 = t plhr485 ? t phlr485 t rr485 90% 0v ?v l a?b ra 10% t phlr485 t fr485 90% 0v ?v ab v ab ?v l 10% v cc
ltc2872 13 2872f t es t circui t s figure 8. rs485 termination resistance and timing measurements (note 5) figure 9. rs232 driver timing and slew rate measurements figure 10. rs232 driver enable and disable times 2872 f08 receiver v ab a b v ab i a r term = v b ?v l ?v l te485 i a i a 90% 10% t rtz485 t rten485 0v v l te485 + ? + ? 2872 f09 driver input driver output c l r l t phld232 t plhd232 t skewd232 = |t phld232 ? t plhd232 | t f t r driver input driver input slew rate = 6v t f or t r 3v ?3v 0v v old v l ?v l ?v l 0v 3v ?3v 0v v ohd 2872 f10 0v or v l dxen driver output c l r l t hzd232 t lzd232 dxen driver output driver output 0.5v t zhd232 t zld232 5v 5v 0.5v 0v 0v 0v v ohd v l ?v l ?v l v old
ltc2872 14 2872f t es t circui t s figure 11. rs232 receiver timing measurements figure 12. rs232 receiver enable and disable times 2872 f11 t phlr232 t skewr232 = |t plhr232 ? t phlr232 | t plhr232 t rr232 90% 1.5v 1.5v ?v l 10% t fr232 90% 0v ?3v v l +3v ?v l 10% 0v v l receiver output receiver output receiver input receiver input c l 2872 f12 ?3v or +3v rxen receiver output gnd or v l c l r l t hzr232 t lzr232 rxen receiver output receiver output 0.5v t zhr232 t zlr232 ?v l ?v l 0.5v 0v 0v v l v ohr v l ?v l ?v l v olr
ltc2872 15 2872f func t ion tables table 1. shutdown and fast enable modes fen 485/232_1 and 485/232_2 rxen1 and rxen2 dxen1 and dxen2 te485_1 and te485_2 h/ f lb dc/dc converter mode and comments 0 x 1 0 0 x x off shutdown: all main functions off 1 x 1 0 0 x x on fast-enable: dc/dc converter on only table 2. mode selection table for a given port (fex = x) 485/232 rxen dxen te485 h/ f lb dc/dc converter mode and comments 0 x 1 x x 0 on rs232 drivers on 0 0 x x x 0 on rs232 receivers on 1 x 1 x x 0 on rs485 driver on 1 0 x x x 0 on rs485 receiver on 1 x x 1 x x on rs485 termination mode (see table 7) 1 x x x 0 0 x rs485 full duplex mode 1 x x x 1 0 x rs485 half duplex mode 1 0 x x x 1 on rs485 loopback mode 0 0 x x x 1 on rs232 loopback mode table 3. rs232 receiver mode for a given port (485/ 232 = 0) rxen receiver input (a, b) conditions receiver outputs (ra, rb) receiver inputs (a, b) 1 x no fault hi-z 125k? 0 0 no fault 1 5k? 0 1 no fault 0 5k? 0 x thermal fault hi-z 5k? table 4. rs232 driver mode for a given port (485/ 232 = 0) dxenx driver input (dy, dz) conditions driver output (y, z) 0 x no fault 125k? 1 0 no fault 1 1 1 no fault 0 x x thermal fault 125k?
ltc2872 16 2872f f unc t ion t ables table 5. rs485 driver mode for a given port (485/ 232 = 1, te485 = 0) dxen dy conditions y z 0 x no fault 125k? 125k? 1 0 no fault 0 1 1 1 no fault 1 0 x x thermal fault 125k? 125k? table 6. rs485 receiver mode for a given port (485/ 232 = 1, lb = 0) rxen aCb (note 5) conditions ra 1 x no fault hi-z 0 < C200mv no fault 0 0 > 200mv no fault 1 0 inputs open or shorted together (dc) no fault 1 x x thermal fault hi-z table 7. rs485 termination for a given port (485/ 232 = 1) te485 dz h/ f , lb conditions r(a to b) r(y to z) 0 x x no fault hi-z hi-z 1 0 x no fault 120? hi-z 1 1 x no fault 120? 120? x x x thermal fault hi-z hi-z table 8. rs485 duplex control for given port (485/ 232 = 1) h/f rs485 driver outputs rs485 receiver inputs 0 y, z a, b 1 y, z y, z table 9. loopback functions for a given port lb rxen transceiver mode 0 x not loopback 1 1 not loopback 1 0 loopback (ra = dy, rb = dz)
ltc2872 17 2872f overview the ltc2872 is a flexible multiprotocol transceiver sup- porting rs485/rs422 and rs232 protocols. it can be powered from a single 3.0v to 5.5v supply with optional logic interface supply as low as 1.7v. an integrated dc/ dc converter provides the positive and negative supply rails needed for rs232 operation. automatically selected integrated termination resistors for both rs232 and rs485 protocols are included, eliminating the need for external components and switching relays. both parts include loopback control for self-test and debug as well as logically-switchable half- and full-duplex control of the rs485 bus interface. the ltc2872 offers two ports that can be independently configured as either two rs232 receivers and drivers or one rs485/rs422 receiver and driver depending on the state of its 485/232 pins. control inputs dxen and rxen provide independent control of driver and receiver opera- tion for either rs232 or rs485 transceivers, depending on the selected operating protocol. the ltc2872 features rugged operation with an esd rating of 15kv hbm on the receiver inputs and driver outputs, both powered and unpowered. all other pins offer protec- tion exceeding 4kv. dc/dc converter the on-chip dc/dc converter operates from the v cc input, generating a 7v v dd supply and a charge pumped C6.3v v ee supply, as shown in figure 13. v dd and v ee power the output stage of the rs232 drivers and are regulated to levels that guarantee greater than 5v output swing. the dc/dc converter requires a 22h inductor (l1) and a bypass capacitor (c4) of 2.2f or larger. the charge pump capacitor (c1) is 470nf and the storage capacitors (c2 and c3) are 2.2f. larger storage capacitors up to 4.7f may be used if c1 and c4 are scaled proportionately. locate c1-c4 close to their associated pins. bypass capacitor c5 on the logic supply pin can be omitted if v l is connected to v cc . see the v l logic supply section for more details about the v l logic supply. inductor selection an inductor with a value of 22h 20% is required. it must have a saturation current (i sat ) rating of at least 200ma and a dcr (copper wire resistance) of less than 1.3. some small inductors meeting these requirements are listed in table 10. table 10. recommended inductors part number l (h) i s at (ma) max dcr () size (mm) manufacturer brc2016t220m cbc2518t220m 22 22 310 320 1.3 1.0 2 1.6 1.6 2.5 1.8 1.8 taiyo yuden t-yuden.com lqh32cn220k53 22 250 0.92 3.2 2.5 1.6 murata murata.com capacitor selection the small size of ceramic capacitors makes them ideal for the ltc2872. use x5r or x7r dielectric types; their esr is low and they retain their capacitance over relatively wide voltage and temperature ranges. use a voltage rating of at least 10v. a pplica t ions i n f or m a t ion figure 13. dc/dc converter with required external components 2872 f13 boost regulator v cc 3v to 5.5v v l 1.7v to v cc c1 470nf l1 22h 21 18 c4 2.2f v cc v dd v ee sw gnd gnd cap c5 0.1f c2 2.2f 19 c3 2.2f 17 20 39 34 v l 35
ltc2872 18 2872f inrush current and supply overshoot precaution in certain applications fast supply slew rates are gener - ated when power is connected. if v cc s voltage is greater than 4.5v and its rise time is faster than 10s, the pins v dd and sw can exceed their absolute maximum values during start-up. when supply voltage is applied to v cc , the voltage difference between v cc and v dd generates inrush current flowing through inductor l1 and capacitors c1 and c2. the peak inrush current must not exceed 2a. to avoid this condition, add a 1 resistor as shown in figure 14. this precaution is not relevant for supply voltages below 4.5v or rise times longer than 10s. by more than 1v for proper operation. logic input pins do not have internal biasing devices to pull them up or down. they must be driven high or low to establish valid logic levels; do not float. rs485 driver the rs485 driver provides full rs485/rs422 compat- ibility. when enabled, if di is high, yCz is positive. when the driver is disabled, y and z output resistance is greater than 96k (typically 125k) to ground over the entire common mode range of C7v to 12v. this resistance is equivalent to the input resistance on these lines when the driver is configured in half-duplex mode and y and z act as the rs485 receiver inputs. driver overvoltage and overcurrent protection the rs232 and rs485 driver outputs are protected from short circuits to any voltage within the absolute maximum range 15v. the maximum current in this condition is 90ma for the rs232 driver and 250ma for the rs485 driver. if an rs485 driver output is shorted to a voltage greater than v cc , when active high, positive current of about 100ma can flow from the driver output back to v cc . if the system power supply or loading cannot sink this excess current, clamp v cc to gnd with a zener diode (e.g., 5.6v, 1w, 1n4734) to prevent an overvoltage condition on v cc . all devices also feature thermal shutdown protection that disables the drivers, receivers, and rs485 terminators in case of excessive power dissipation (see note 6). rs485 balanced receiver with full failsafe support the ltc2872 rs485 receiver has a differential threshold voltage that is about 80mv for signals that are rising and C80mv for signals that are falling, as illustrated in figure 15. if a differential input signal lingers in the win - dow between these thresholds for more than about 2s, the rising threshold changes from 80mv to C50mv, while the falling threshold remains at C80mv. thus, differential inputs that are shorted, open, or terminated but not driven for more than 2s produce a high on the receiver output, indicating a failsafe condition. a pplica t ions i n f or m a t ion figure 14. supply current overshoot protection for input supplies of 4.5v of higher v l logic supply a separate logic supply pin v l allows the ltc2872 to interface with any logic signal from 1.7v to 5.5v. all logic i/os use v l as their high supply. for proper operation, v l should not be greater than v cc . during power-up, if v l is higher than v cc , the device will not be damaged, but behavior of the device is not guaranteed. if v l is not con- nected to v cc , bypass v l with a 0.1f capacitor. rs232 and rs485 driver outputs are undriven and the rs485 termination resistors are disabled when v l or v cc is grounded or v cc is disconnected. although all logic input pins reference v l as their high supply, they can be driven up to 7v, independent of v l and v cc , with the exception of fen, which must not exceed v l 2872 f14 0v 5v 10s c1 470nf l1 22h inrush current c4 2.2f r1 1 1/8w v cc v dd gnd sw 19 17 cap 20 21 18 c2 2.2f
ltc2872 19 2872f figure 15. rs485 receiver input threshold characteristics with typical values shown a pplica t ions i n f or m a t ion the benefit of this dual threshold architecture is that it supports full failsafe operation yet offers a balanced threshold, centered on 0v, for normal data signals. this balance preserves duty cycle for small input signals with heavily slewed edges, typical of what might be seen at the end of a very long cable. this performance is highlighted in figure 16, where a signal is driven through 4000 feet of cat5e cable at 3mbps. even though the differential signal peaks at just over 100mv and is heavily slewed, the output maintains a nearly perfect signal with almost no duty cycle distortion. lines, which establishes a logic-high state when all the transmitters on the network are disabled. the values of the biasing resistors depend on the number and type of transceivers on the line and the number and value of terminating resistors. therefore, the values of the biasing resistors must be customized to each specific network installation, and may change if nodes are added to or removed from the network. the internal failsafe feature of the ltc2872 eliminates the need for external network biasing resistors provided they are used in a network of transceivers with similar internal failsafe features. this also allows the network to support a high number of nodes, up to 256, by eliminating the bias resistor loading. the ltc2872 transceivers will operate correctly on biased, unbiased, or under-biased networks. receiver outputs the rs232 and rs485 receiver outputs are internally driven high (to v l ) or low (to gnd) with no external pull-up needed. when the receivers are disabled, the output pin becomes hi-z with leakage of less than 5a for voltages within the v l supply range. rs485 receiver input resistance the rs485 receiver input resistance from a or b to gnd (y or z to gnd in half-duplex mode with driver disabled) is greater than 96k (typically 125k) when the integrated termination is disabled. this permits up to a total of 256 receivers per system without exceeding the rs485 receiver loading specification. the input resistance of the receiver is unaffected by enabling/disabling the receiver or whether the part is in half-duplex, full-duplex, loopback mode, or even unpowered. the equivalent input resistance looking into the rs485 receiver pins is shown in figure 17. figure 16. a 3mbps signal driven down 4000ft of cat5e cable. top traces: received signals after transmission through cable; middle trace: math showing differences of top two signals; bottom trace: receiver output an additional benefit of the balanced architecture is excel - lent noise immunity due to the wide effective differential input signal hysteresis of 160mv for signals transitioning through the window region in less than 2s. increasingly slower signals will have increasingly less effective hyster - esis, limited by the dc failsafe hysteresis of about 30mv. rs485 biasing network not required rs485 networks are often biased with a resistive divider to generate a differential voltage of 200mv on the data 0.1v/div 0.1v/div 5v/div 2872 f16 200ns/div ra (a-b) a b figure 17. equivalent rs485 receiver input resistance into a and b (note 5) 2872 f17 a b te485 60 60 125k 125k 2872 f15 ?80mv ?50mv 0v ra 80mv v ab (note 5) rising threshold shifts if signal is in window > ~2s to support failsafe
ltc2872 20 2872f a pplica t ions i n f or m a t ion selectable rs485 termination proper cable termination is important for good signal fidel- ity. when the cable is not terminated with its characteristic impedance, reflections cause waveform distortion. the ltc2872 offers integrated switchable 120 termination resistors between the differential receiver inputs and also between the differential driver outputs. this provides the advantage of being able to easily change, through logic control, the proper line termination for correct operation when configuring transceiver networks. termination should be enabled on transceivers positioned at both ends of a network bus. termination on the driver nodes is important for cases where the driver is disabled but there is communication on the connecting bus from another node. driver termination across y and z can be disabled independently from the termination across a and b by setting dz low. see table 7 for details. the termination resistance is maintained over the entire rs485 common mode range of C7v to 12v as shown in figure 18. the voltage across pins with the terminating resistor enabled should not exceed 6v as indicated in the absolute maximum ratings table. figure 18. typical resistance of the enabled rs485 terminator vs common mode voltage of a and b the differential receiver inputs. with the h/f pin set to a logic-high, the y and z pins serve as the differential inputs. in either configuration, the rs485 driver outputs are always on y and z. the impedance looking into the a and b pins is not affected by h/f control, including the differential termination resistance. the h/f control does not affect rs232 operation. logic loopback a loopback mode connects the driver inputs to the re- ceiver outputs (noninverting) for self test. this applies to both rs232 and rs485 transceivers. loopback mode is entered when the lb pin is set to a logic-high and the relevant receiver is enabled. in loopback mode, the drivers function normally. they can be disabled with output in a hi-z state or left enabled to allow loopback testing in normal operation. loopback works in half- or full-duplex modes and does not affect the termination resistors. rs485 cable length vs data rate many factors contribute to the maximum cable length that can be used for for rs485 or rs422 communication, including driver transition times, receiver threshold, duty cycle distortion, cable properties and data rate. a typical curve of cable length versus maximum data rate is shown in figure 19. various regions of this curve reflect different performance limiting factors in data transmission. figure 19. cable length vs data rate (rs485/rs422 standard shown in vertical solid line) rs485 half- and full-duplex control the ltc2872 is equipped with a control to change the rs485 transceiver operation from full-duplex to half-duplex. with the h/f pin set to a logic-low, the a and b pins serve as data rate (bps) cable length (ft) 2872 f19 10k 1k 100 10 10k 10m 100m 1m 100k ltc2872 max data rate rs485/rs422 max data rate voltage (v) ?10 resistance () 126 124 122 118 120 116 10 ?5 2872 f18 15 50 v cc = 5.0v v cc = 3.3v
ltc2872 21 2872f a pplica t ions i n f or m a t ion at frequencies below 100kbps, the maximum cable length is determined by dc resistance in the cable. in this ex- ample, a cable longer than 4000ft will attenuate the signal at the far end to less than what can be reliably detected by the receiver. for data rates above 100kbps, the capacitive and inductive properties of the cable begin to dominate this relation- ship. the attenuation of the cable is frequency and length dependent, resulting in increased rise and fall times at the far end of the cable. at high data rates or long cable lengths, these transition times become a significant part of the signal bit time. jitter and intersymbol interference aggravate this so that the time window for capturing valid data at the receiver becomes impossibly small. the boundary at 20mbps in figure 19 represents the guaranteed maximum operating rate of the ltc2872. the dashed vertical line at 10mbps represents the specified maximum data rate in the rs485 standard. this boundary is not a limit, but reflects the maximum data rate that the specification was written for. it should be emphasized that the plot in figure 19 shows a typical relation between maximum data rate and cable length. results with the ltc2872 will vary, depending on cable properties such as conductor gauge, characteristic impedance, insulation material, and solid versus stranded conductors. layout considerations all v cc pins must be connected together and all ground pins must be connected together on the pc board with very low impedance traces or dedicated planes. a 2.2f, or larger, bypass capacitor should be placed less than 0.7cm away from v cc pin 21. this v cc pin, as well as gnd pin 18, mainly service the dc/dc converter. additional bypass capacitors of 0.1f or larger, can be added to v cc pins 1 and 31 if the traces back to the 2.2f capacitor are indirect or narrow. these v cc pins mainly service the transceivers #1 and #2, respectively. table 11 summarizes the bypass capacitor requirements. the capacitors listed in the table should be placed closest to their respective supply and ground pin. table 11. bypass capacitor requirements capacitor supply (pin) return (pin) comment 2.2f v cc (21) gnd (18) required 2.2 f v dd (20) gnd (18) required 2.2uf v ee (39) gnd (18) required 0.1f v l (35) gnd (34) required* 0.1f v cc (1) gnd (5) optional 0.1f v cc (31) gnd (27) optional * if v l is not connected to v cc . place the charge pump capacitor, c1, directly adjacent to the sw and cap pins, with no more than one centimeter of total trace length to maintain low inductance. close placement of the inductor, l1, is of secondary importance compared to the placement of c1 but should include no more than two centimeters of total trace length. the pc board traces connected to high speed signals a/b and y/z should be symmetrical and as short as possible to minimize capacitive imbalance and to maintain good differential signal integrity. to minimize capacitive loading effects, the differential signals should be separated by more than the width of a trace and should not be routed on top of each other if they are on different signal planes. care should be taken to route outputs away from any sen- sitive inputs to reduce feedback effects that might cause noise, jitter, or even oscillations. for example, di and a/b should not be routed near the driver or receiver outputs.
ltc2872 22 2872f typical a pplica t ions figure 20. ltc2872 in various basic port configurations figure 21. loopback in rs232 and rs485 modes figure 22. half-duplex rs485 mode with driver and receiver line termination on each port figure 23. full-duplex rs485 mode with driver and receiver line termination on port 1, and receiver- only termination on port 2 v l dy1 dz1 y1 z1 ra1 rb1 a1 b1 dy2 y2 z2 ra2 a2 b2 2872 f21 ltc2872 lb 485/232_2 485/232_1 rxen1 rxen2 h/f gnd v l 2872 f22 ltc2872 h/f te485_1 te485_2 485/232_1 485/232_2 dz1 dz2 lb gnd dy1 120 y1 z1 ra1 a1 b1 120 dy2 120 y2 z2 ra2 a2 b2 120 v l 2872 f23 ltc2872 te485_1 te485_2 dz1 485/232_1 485/232_2 dz2 h/f lb gnd dy2 y2 z2 ra2 a2 b2 120 dy1 y1 z1 ra1 a1 b1 120 120 v cc = 3v to 5.5v, v l = 1.7v to v cc . logic input pins not shown are tied to a valid logic state. external components necessary for operation are not shown. 2872 f20 485/232_1 485/232_2 lb dy1 dz1 y1 z1 ra1 rb1 a1 b1 dy2 dz2 y2 z2 ra2 rb2 a2 b2 ltc2872 port 1: rs232 port 2: rs232 port 1: rs232 port 2: rs485 port 1: rs485 port 2: rs232 port 1: rs485 port 2: rs485 dy1 dz1 y1 z1 ra1 rb1 a1 b1 dy2 y2 z2 ra2 a2 b2 ltc2872 485/232 _2 485/232_1 h/f lb gnd dy2 dz2 y2 z2 ra2 rb2 a2 b2 dy1 y1 z1 rb1 a1 b1 ltc2872 485/232 _1 485/232_2 h/f lb gnd dy1 v l v l v l y1 z1 ra1 a1 b1 ltc2872 485/232_1 485/232_2 h/f lb gnd dy2 y2 z2 ra2 a2 b2
ltc2872 23 2872f t ypical a pplica t ions figure 24. typical rs485 half duplex network 2872 f25 ? ltc2872 master 120 ? ltc2872 ? ltc2872 slave te485 h/f te485 dz h/f te485 dz h/f v l v l 120 120 figure 25. typical rs485 full duplex network 2872 f24 ? ltc2872 120 ? ltc2872 ? ltc2872 te485 h/f te485 dz h/f te485 dz h/f v l v l v l 120 v cc = 3v to 5.5v, v l = 1.7v to v cc . logic input pins not shown are tied to a valid logic state. external components necessary for operation are not shown.
ltc2872 24 2872f t ypical a pplica t ions figure 26. rs485 receiver with 4-way selectable inputs 2872 f26 h/f ra1 rxen1 rs485 interface input1 input2 y1 z1 a1 b1 ltc2872 s3 h/f ra2 rxen2 input3 input4 y2 z2 a2 b2 s1 output s2 s2 1 1 0 0 1 0 s1 0 0 1 1 1 0 selected input input1 input2 input3 input4 none/hi-z invalid s3 1 0 1 0 x x v cc = 3v to 5.5v, v l = 1.7v to v cc . logic input pins not shown are tied to a valid logic state. external components necessary for operation are not shown.
ltc2872 25 2872f t ypical a pplica t ions figure 27. sharing rs232 receiver inputs figure 28. low voltage microprocessor interface 2872 f27 ra1 a1 a2 rxen1 rs232 input * does not meet rs232 specifications r in ra2 rxen2 s1 out1 out2 ltc2872 ?or? s2 s2 1 0 1 0 s1 0 1 1 0 active output out1 out2 none (hi-z) out1, out2 r in 5k 5k 62.5k 2.5k* rb1 b1 b2 rxen1 rs232 input r in rb2 rxen2 s1 out1 out2 ltc2872 s2 2872 f28 3v to 5.5v 1.7v to v cc p ltc2872 logic level signals line level signals rs232 and/or rs485 v cc v l gnd v cc = 3v to 5.5v, v l = 1.7v to v cc . logic input pins not shown are tied to a valid logic state. external components necessary for operation are not shown.
ltc2872 26 2872f figure 29. rs232 ? rs485 conversion figure 30. rs485 repeater t ypical a pplica t ions 2872 f29 ltc2872 dy2 ra1 ra2 y2 a1 rs485 out rs485 in rs232 in rs232 out y1 z2 a2 b2 dy1 120 2872 f29 ltc2872 dy2 ra1 ra2 y2 z2 a2 b2 a1 b1 y1 z1 dy1 120 120 120 120 v cc = 3v to 5.5v, v l = 1.7v to v cc . logic input pins not shown are tied to a valid logic state. external components necessary for operation are not shown.
ltc2872 27 2872f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc2872 28 2872f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0312 ? printed in usa r ela t e d p ar t s typical a pplica t ion figure 31. ltc2872 on left: rs485 half-duplex and terminated, plus rs232. ltc2872 on right: dual rs485 half-duplex and terminated. all external components shown part number description comments ltc2870/ltc2871 rs232/rs485 multiprotocol transceivers with integrated termination 3v to 5.5v supply, automatic selection of termination resistors, duplex control, logic supply pin, 26kv esd ltc1334 single 5v rs232/rs485 multiprotocol transceiver dual port, single 5v supply, configurable, 10kv esd ltc1387 single 5v rs232/rs485 multiprotocol transceiver single port, configurable ltc2801/ltc2802/ ltc2803/ltc2804 1.8v to 5.5v rs232 single and dual transceivers up to 1mbps, 10kv esd, logic supply pin, tiny dfn packages ltc2854/ltc2855 3.3v 20mbps rs485 transceiver with integrated switchable termination 3.3v supply, integrated, switchable, 120 termination resistor, 25kv esd ltc2859/ltc2861 20mbps rs485 transceiver with integrated switchable termination 5v supply, integrated, switchable, 120 termination resistor, 15kv esd LTM2881 complete isolated rs485/rs422 module ? transceiver + power 20mbps, 2500v rms isolation with integrated dc/dc converter, integrated switchable 120 termination resistor, 15kv esd ltm2882 dual isolated rs232 module transceiver + power 1mbps, 2500v rms isolation with integrated dc/dc converter, 10kv esd 2872 f31 5v 1.8v v l 485/232_1 te485_1 dz1 h/f 485/232_2 te485_2 lb gnd v cc sw 22h 470nf cap ltc2872 ltc2872 rs485 cat5e cable dyi ra1 z1 y1 z1 a1 b1 dy1 ra1 dy2 dz2 ra2 ra2 v dd v ee y2 z2 a2 a2 y1 120 120 2.2f 0.1f 2.2f 2.2f rs232 3.3v interface 1.8v interface v dd v ee 2.2f 2.2f v l 485/232_1 485/232_2 te485_1 te485_2 dz1 h/f dz2 lb gnd 3.3v v cc sw 22h 470nf cap 2.2f 120 a1 b1 120 dy2 ra2 z2 y2 a2 b2 120

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